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TMS320C5515
SPRS645F – AUGUST 2010 – REVISED OCTOBER 2013
www.ti.com
2.5.6
I2S0 – I2S3 Terminal Functions
Table 2-10. Inter-IC Sound (I2S0 – I2S3) Terminal Functions
SIGNAL
NAME
NO.
TYPE (1)
(2)
OTHER (3)
(4)
DESCRIPTION
Interface 0 (I2S0)
This pin is multiplexed between MMC0, I2S0, and GPIO.
MMC0_D0/
I2S0_DX/
GP[2]
L9
I/O/Z
IPD
DV DDIO
BH
For I2S, it is I2S0 transmit data output I2S0_DX.
Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR1 register.
This pin is multiplexed between MMC0, I2S0, and GPIO.
MMC0_CLK/
I2S0_CLK/
GP[0]
L10
I/O/Z
IPD
DV DDIO
BH
For I2S, it is I2S0 clock input/output I2S0_CLK.
Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR1 register.
This pin is multiplexed between MMC0, I2S0, and GPIO.
MMC0_D1/
I2S0_RX/
GP[3]
M10
I/O/Z
IPD
DV DDIO
BH
For I2S, it is I2S0 receive data input I2S0_RX.
Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR1 register.
This pin is multiplexed between MMC0, I2S0, and GPIO.
MMC0_CMD/
I2S0_FS/
GP[1]
M11
I/O/Z
IPD
DV DDIO
BH
For I2S, it is I2S0 frame synchronization input/output I2S0_FS.
Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR1 register.
Interface 1 (I2S1)
This pin is multiplexed between MMC1, I2S1, and GPIO.
MMC1_D0/
I2S1_DX/
GP[8]
M14
I/O/Z
IPD
DV DDIO
BH
For I2S, it is I2S1 transmit data output I2S1_DX.
Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR1 register.
This pin is multiplexed between MMC1, I2S1, and GPIO.
MMC1_CLK/
I2S1_CLK/
GP[6]
M13
I/O/Z
IPD
DV DDIO
BH
For I2S, it is I2S1 clock input/output I2S1_CLK.
Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR1 register.
This pin is multiplexed between MMC1, I2S1, and GPIO.
MMC1_D1/
I2S1_RX/
GP[9]
M12
I/O/Z
IPD
DV DDIO
BH
For I2S, it is I2S1 receive data input I2S1_RX.
Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR1 register.
This pin is multiplexed between MMC1, I2S2, and GPIO.
MMC1_CMD/
I2S1_FS/
GP[7]
L14
I/O/Z
IPD
DV DDIO
BH
For I2S, it is I2S1 frame synchronization input/output I2S1_FS.
Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR1 register.
(1)
(2)
(3)
(4)
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder
Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to
float. When they are configured as input or high-impedance state, and not driven to a known state, they may cause an excessive IO-
supply current. Prevent this current by externally terminating it or enabling IPD/IPU, if applicable.
IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.8.1 , Pullup/Pulldown Resistors .
Specifies the operating I/O supply voltage for each signal
26
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